The present invention relates to a semiconductor integrated circuit device and a process for manufacturing the same and, more particularly, to a technique which is effective if applied to a semiconductor integrated circuit device having its elements separated by a separating groove formed in a semiconductor substrate.
More specifically, the present invention relates to a technique which is effective if applied to the type of semiconductor integrated circuit device in which bipolar transistors and complementary MOSFETs (which will be referred to as the "CMOS") are formed in a silicon single crystal layer laid over an insulating layer and in which the bipolar transistors are surrounded by an insulating separating groove, whereas the NMOS and the PMOS are separated by a separating groove.
In recent years, the bipolar devices or bipolar CMOS devices applied to a fast memory LSI or a fast logic LSI are intended to reduce the parasitic capacity and to improve the degree of integration by separating the elements by a separating groove formed in the semiconductor substrate.
FIG. 12 is a top plan view of an essential portion of a semiconductor substrate and shows a general construction of the bipolar device, and FIG. 13 is a section taken along line B-B' of FIG. 12. Reference numerals 30, 31 and 32 appearing in those Figures designate a p-type semiconductor substrate, an n.sup.+ -type buried layer and an n-type epitaxial layer.
In the Figures, the bipolar transistor is formed in the region surrounded by a field oxide film 41, with the aforementioned buried layer 31 as its buried type heavily doped collector region, the epitaxial layer 32 as its lightly doped collector region, an n-type semiconductor region 33 as its collector contact region, a p-type semiconductor region 34 as its base region, and an n.sup.+ -type semiconductor region 35 as its emitter region, and is electrically isolated from an adjoining element by a groove 36 enclosing it. An insulator 40 is buried in the groove 36. The emitter region 35, the base region 34 and the collector contact region 33 are respectively connected with an emitter electrode 37, a base electrode 38 and a collector electrode 39, which are made of Al, for example, through the openings formed in an inter-layer insulating film 42.
In FIG. 6 on pp. 68 of "Bi-CMOS Technology and Applications" of 1989 published by Kluwer Academic Publication and edited by Antonio R. Alvarez, there is disclosed the Bi-CMOS process of forming an n-type buried layer and a p-type buried layer on the surface of a p-type silicon substrate, forming an n-type epitaxial layer on the p-type silicon substrate, and subsequently forming an n-type well region and a p-type well region in the n-type epitaxial layer positioned over the aforementioned n-type buried layer and p-type buried layer. There is another disclosure, in which a thick field insulating film is formed in the boundary between the n-type well region and the p-type well region so that it may be used as an isolation region between the NMOS elements or the PMOS elements.
Moreover, the bipolar transistors are electrically isolated from each other by the separating groove which extends from the surface of the n-type epitaxial layer to separate the n-type buried layer.
In Japanese Patent Laid-Open No. 184068/1990, there is disclosed a process of forming an n-type well region and a p-type well region over a silicon substrate (i.e., Silicon On Insulator substrate, as will be shortly referred to as the "SOI substrate") formed over an insulating layer, subsequently forming an isolation groove between the aforementioned n-type well region and p-type well region, and forming a CMOS over the main surface of each of the n-type well region and the p-type well region isolated by the aforementioned isolation groove.